This invention relates generally to rules checking, and more particularly to a methodology for reducing the computer storage required to perform an Electrical Rules Check (ERC) of a digital circuit design.
An electrical circuit, such as a digital circuit design, may be thought of as having one or more elements and one or more nodes that serve as connection points to the elements. A node may serve as an interconnection point between two or more electrical elements. A node may additionally be considered a connection point that connects an element to something else; for instance, a node may serve as a connection point to an external environment in which the circuit is situated, such as an input or output point of the circuit. In light of these definitions of a node, it is possible to have a circuit design that has only one element and one node, two or more elements and one or more nodes, or one or more elements and two or more nodes, etc. In digital circuit design, nodes commonly connect electrical elements such as transistors and resistors. A netlist, or external representation of the circuit, simply specifies the physical interconnections or nodes between the electrical elements without providing information about various electrical parameters or measurements at those nodes. A netlist, then, is by itself insufficient to provide needed information about the nodes of an electrical circuit.
ERC software is often used to analyze electrical circuit design during design and implementation phases. It is critical to the successful implementation of an electrical circuit that certain information about elements and nodes be stored for use during ERC analysis of the circuit design. Each element in the circuit design requires storage that is used to record its connections to design nodes, generally referred to herein as element information. Similarly, each node requires storage that is used to record its timing characteristics and coupling information and interconnectivity information to other nodes and/or elements, generally referred to herein as node information. The amount of information that must be recorded for elements and nodes can vary greatly and is somewhat dependent upon the type of element or node in questions. Nodes that have connections to resistor elements, for example, have no timing or coupling information that is used in the Electrical Rule Checking of the circuit design; therefore the storage space allocated for timing and coupling information for a node having connections to resistor element is unused. Resistor elements have only two node connections while transistor elements have six, and perhaps more, node connections that must be stored.
In spite of the different amounts of information required for elements and nodes, however, the amount of computer storage space allocated for nodes and elements of a circuit design is typically consistent and thus impervious to variations in the amount of information that needs to be stored for various types of nodes and elements. Thus, a significant amount of the storage space allocated for node connection information of resistor elements is unused. This wasted computer storage can be especially significant for large, complex electrical designs such as Very Large Scale Integration (VLSI) integrated circuits (ICs). Suppose, for instance, that a design has 100,000 transistors and 1,000,000 resistors. Traditional space allocation makes no distinction between transistor elements and resistor elements and the amount of space allocated for each resistor and transistor will be the same. The storage space allocated for the million resistors will be largely wasted since the mount of information necessary to store for the resistors is much less than the amount of information necessary to store for transistors. The resistor storage space will thus be underutilized. There is therefore an unmet need in the art to reduce the size of computer storage that is required to perform an Electrical Rules Check (ERC) of a circuit design. Reducing the amount of storage would result in cost savings and increases in inefficiency of the ERC process.
It is therefore an object of the present invention to reduce the computer storage required to perform an Electrical Rules Check (ERC) of a digital circuit design.
Therefore, according to the present invention, a rules checking methodology analyzes an electrical circuit characterized as having one or more elements and one or more nodes, the xe2x80x9cstructuresxe2x80x9d of the circuit. Of particular interest to the methodology of the present invention is the creation of up to four different types of data structures specific to the type of element or node being analyzed. Thus, for each structure of the circuit, whether it be a node, a small node defined as being interconnected only to resistors, a non-resistor element, or a resistor element, a data structure representative of the structure is created. Creating the data structure includes creating a link of the data structure and filling one or more data fields with information specific to the structure; the information of the data fields is stored in a storage element, such as memory, and is used by one or more processors that run an ERC program which analyzes the electric circuit. The created data structure is placed in an appropriate linked list; a node data structure is placed in a node linked list, a small node data structure is placed in a small node linked list, a non-resistor element data structure is placed in a non-resistor element linked list, and a resistor element data structure is placed in a resistor element linked list.
The structures of the circuit are next analyzed by analyzing the data structures thus created and placed in appropriate linked lists by the one or more processors running the ERC program; the information stored in the data fields of the data structures are utilized by the program during the analysis. Analysis of the structures by the one or more processors may take place sequentially or in parallel. Prior to analysis, known topology types of the circuit may optionally be searched for and extracted. Following analysis, the information stored in the storage element about one or more data structures may be changed and the circuit re-analyzed in accordance with the changed information in order to enhance analysis of the circuit. The results of the analysis and/or the re-analysis of the circuit may be reported if desired. The methodology of the present invention may be implemented by a storage media containing the computer program for performing the ERC of the electrical circuit.